We are very excited about all aspects of the symposium, especially the technical sessions. We received 61 submissions of remarkably high caliber. Each submission was reviewed by at least 5 leading experts in the field. The selection process was very challenging; only after many email discussions could the program committee finally settle on accepting the 23 papers included in the proceedings.

This year we plan to ``spice'' up the technical part of the presentations by devoting 15 minutes at the end of each technical session for a short debate on a related controversial topic. It is our hope that these debates invoke more open exchange of ideas among all participants - the presenters and the audience alike. The technical program also contains a plenary session, a tutorial, a keynote address, a panel session, and a demo session. The program starts with a plenary session by Prof. Stephen Unger (Columbia) who will provide us with an historical survey of asynchronous circuits. Prof. Unger, one of the pioneers of this field, will perhaps shed some light on the future by providing us a historical perspective. Dr. Ivan Sutherland (Sun Microsystems Lab) will give a tutorial on issues at the boundary between synchronous and asynchronous systems. The Keynote Address will be given by Prof. Mark Horowitz (Stanford) on clocking high-performance processors. Prof. Horowitz will address the advantages and disadvantages of both synchronous and asynchronous circuits. The panel session will focus on the next-generation asynchronous design methodologies.

To provide a relaxing atmosphere for interaction with colleagues, we interspersed several "social'' activities within the program. On Monday (March 30), we will have a tour of Qualcomm, one of the leaders of the wireless industry. On Tuesday, we will have a brief excursion to the historic Hotel Del Coronado in the afternoon. On Wednesday, there will be an outdoor banquet (California Beach Party). We would like to thank everyone who helped make this symposium possible. In particular, we would like to thank all the program committee members for their professional and thorough paper reviews and discussions, senior committee members for their helpful advice, panel members and session chairs for the active participation, and Kristine Kelly at the IEEE Computer Society Press for helping us with proceedings. We would especially like to thank Patricia Campbell for the superb job she has done ``running'' the symposium. We are grateful to the University of California, San Diego and Intel Corp. for their financial support and Qualcomm Inc. for the interesting tour.

Peter Beerel, University of Southern California

Kenneth Yun, University of California, San Diego

A major goal of the symposium is to identify application domains where asynchronous circuit techniques are of practical interest and to articulate, quantify, and demonstrate their potential advantages (such as high speed, low power, low EM radiation, and high reliability). Special emphasis will be given to industrial applications, functional ICs, and mature CAD tools. Furthermore, we are interested in exploring technical innovations that may help improve the cost, quality, performance, or testability of the final product.

Dr. Horowitz's research area is in digital system design, and he has led a number of processor designs including MIPS-X, one of the first processors to include an on-chip instruction cache, TORCH, a statically-scheduled, superscalar processor and FLASH, a flexible DSM machine. He has also worked in a number of other chip design areas including high-speed memory design, high-bandwidth interfaces, and fast floating point. In 1990 he took leave from Stanford to help start Rambus Inc, a company designing high-bandwidth memory interface technology. His current research includes multiprocessor design, low power circuits, memory design, and high-speed links.