Announcements

Dec 8: Check here for group assignment.

Nov 30: Check here for updates on final project information. This page will be continuously updated, so please check routinely.

Nov 16: Check out a sample midterm.

Nov 2: Use 8:2 for both pMOS and nMOS for MAGIC layout in PS3.

Final project

Nov 2: Problem set 3 due Tuesday, November 16.

Oct 28: Use the non-inverting static latch discussed in the class for PS2. Assume that only the following gates are available in the library: NAND2, NAND3, NOR2, NOR3, INV, INVP, and LATCH. For INVP, W/L's of pMOS and nMOS are 64:2 and 32:2 respectively. For all other gates except LATCH, W/L's of pMOS and nMOS are 16:2 and 8:2 respectively.

Oct 20: Espresso (two-level logic minimizer) references [here].

Oct 20: Check here for IRSIM tuturial. IRSIM as well as PS2 will be discussed in the discussion section on Oct 27.

Oct 20: Problem set 2 due Tuesday, November 2.

Oct 17: Class notes are also available in PDF format.

Oct 15: Ayoob will be in the lab between 7 and 8pm on Monday (Oct 18) to help you with any Mentor or PS1 problems.

Oct 15: There will be no discussion session this Wednesday (Oct 20).

Oct 9: Problem set 1 due Tuesday, October 19.

Oct 7: Next Tuesday's lecture (Oct 12) will be a Mentor demo/hands-on session held in 3329 EBU1. Ayoob Dooply will be the instructor for the demo/hands-on session. Please go straight to 3329 EBU1; do not show up in HSS.

Oct 6: Discussion sections will be on Wednesdays between 4:40 and 5:30pm in WLH 2207, starting next week (Oct. 13).

Downloading lecture notes: your best bet is to use Internet Explorer 5 (IE5) on PCs running Windows 95/98/NT.

Lecture Notes and Problem Sets

Instructions on how to download Acroread from Adobe, which is a free PDF viewer

Information on how to obtain Ghostview (a Postscript viewer)

VLSI digital systems. Circuit analysis and optimization. Circuits for various logic styles and clocking schemes. Control and datapath. Design and simulation using CAD tools.

Tentative Course Syllabus

Prof. Kenneth Y. Yun

Office hours: TTh 5:30pm-6:30pm, 4402 EBU1

Phone: (858) 534-6365

E-mail: kyy@paradise.UCSD.EDU

Teaching Assistant

Kirk Miller

• E-mail: kamiller@UCSD.EDU
• Office: 2317 EBU1 Ph: (858) 534-9847
• Hours: TBD, (2317,3329) EBU1

  Office hours will be held in EBU1 2317 unless posted otherwise.

Class Schedule

Lectures: TTh 3:55-5:15pm, HSS 2305A

Discussion: W 4:40-5:30pm, WLH 2207

Textbooks

Optional: Principles of CMOS VLSI Design, Second Edition by Weste and Eshraghian

Prerequisites

ECE 108 or instructor's consent

Logic design (ECE 20B/30 or CSE 140/140L level)

Tentative Exam and Grading Plan

Problem Sets: 30%

• Due one week after handout; solutions will be available one week after the due dates.
• 25% penalty for late homeworks up to the time solutions are handed out.

Midterm: 25%

• Thursday, Nov 18 in class

Final Project: 45%

• Checkoff and report due 6pm, Tuesday, Dec 14

Computer Usage

WWW browser:

• To browse or retrieve course information, handouts and problem sets. Dissemination of course information will be entirely Web-centric, i.e., the class Web page is the official source of up-to-date class annoucements.

CAD tools: Mentor Design Architect, Accusim, MAGIC, and IRSIM

• Available at ACS workstation lab (EBU-I 3327/3329).
• You can download a PC version of MAGIC/IRSIM for home usage. The only version compatible with this class usage is MAGIC 6.4 which runs on PCs running Linux. ECE 260B teaching staff will offer NO support for this version.