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Asynchronous circuits and systems are gaining widespread interest because of their inherently lower power and potentially higher performance advantages over conventional synchronous circuits. This course reviews recent research results in asynchronous VLSI circuits and systems, in particular, practical designs and design methodologies. Some of the topics to be covered are:

1. Micropipelines;
2. Generalized fundamental-mode controllers;
3. Mixed-timing circuits for synchronous / asynchronous interfaces;
4. Asynchronous datapath.

Prof. Kenneth Y. Yun

Office hours: TBD, 4402 EBU1

Phone: 534-6365

E-mail kyy@paradise.UCSD.EDU

Teaching Assistant

Ayoob Dooply

E-mail adooply@UCSD.EDU

Office hours: TBD

Class Schedule

Lecture: TTh 2:20-3:40pm, U413A Room 1

Prerequisites

ECE 260B or instructor's consent

Hands-on knowledge of Mentor design automation tools

Tentative Course Syllabus

Week	Topic
1	Asynchronous design overview
2	Micropipelines I
3	Micropipelines II
4	Burst-mode controllers
5	Hazard-free logic synthesis
6	Asynchronous processor design I
7	Asynchronous processor design II
8	Synchronous / asynchronous interface
9	Verification
10	Design examples

Tentative Grading Plan

Project: 50%

Midterm: 30%

Participation: 20%

Reading

Course reader to be available at QuikPrint, 4150 Regents Park Row #130 (457-1007)

Overview

"Asynchronous design methodologies: An overview," Scott Hauck. In Proceedings of the IEEE, 83(1):69-93, 1995. [PDF] [Postscript]

Micropipelines

"Micropipelines," Ivan Sutherland. In Communications of the ACM, 32(6):720-738, 1989.

"Investigations into Micropipeline Latch Design Styles," P. Day and J. V. Woods. In IEEE Transactions on VLSI Systems, 3(2):264-272, June 1995.

"Four-Phase Micropipeline Latch Control Circuits," S. B. Furber and P. Day. In IEEE Transactions on VLSI Systems, 4(2):247-253, June 1996.

"Dynamic Logic in Four-Phase Micropipeline," S. B. Furber and J. Liu. In Proceedings of ASYNC'96, pages 11-16.

"High-performance two-phase micropipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits," K. Y. Yun, P. A. Beerel, and J. Arceo. In IEE Proceedings-Circuits, Devices and Systems, pages 282-288, Vol. 143, No. 5, October 1996.

Burst-mode controllers and hazard-free synthesis

"Exact two-level minimization of hazard-free logic with multiple-input changes," S. M. Nowick and D. L. Dill. In IEEE Transactions on Computer-Aided Design, 14(8):986-997, August 1995.

"Synthesis of 3D asynchronous state machines," K. Y. Yun, S. M. Nowick, and D. L. Dill. In Proceedings of ICCD'92, pages 346-350. [PDF] [Postscript]

"Unifying synchronous/asynchronous state machine synthesis," K. Y. Yun and D. L. Dill. In Proceedings of ICCAD'93, pages 255-260. [PDF] [Postscript]

"Automatic synthesis of extended burst-mode circuits using generalized C-elements," Kenneth Yun. In Proceedings of EURODAC'96, pages 290-295. [PDF] [Postscript]

Asynchronous processor design

"AMULET1: An Asynchronous ARM Microprocessor," J. V. Woods, P. Day, S. B. Furber, J. D. Garside, N. C. Paver, S. Temple. In IEEE Transactions on Computers, 46(4):385-398, April 1997.

"AMULET2e: An Asynchronous Embedded Controller," S. B. Furber, J. D. Garside, S. Temple, J. Liu. In Proceedings of ASYNC'97, pages 290-299.

"The AMULET2e Cache System," J. D. Garside, S. Temple, and R. Mehra. In Proceedings of ASYNC'96, pages 208-217. [PDF]

[Postscript]

"The counterflow pipeline processor architecture," R. F. Sproull, I. E. Sutherland, and C. E. Molnar. In IEEE Design and Test of Computers, 11(3):60-69, 1994.

Computer Labs, Accounts, and Usage

Computer Lab

HP Lab: EBU1 6501

SUN Lab: EBU1 3329

Every student must have an OCE account and should be familiar with UNIX operating system and X window.

Web browser to browse or retrieve course information, handouts and problem sets.

Mentor Design Automation Package and other design tools for design projects.

WWW Tutorial

On-line tutorial of WWW