Recent Publications of Kenneth Yun

  1. K. Y. Yun, K. W. James, R. H. Fairlie-Cuninghame, S. Chakraborty, and R. L. Cruz, "A self-timed real-time sorting network," to appear in IEEE Transactions on VLSI Systems, Mar. 2000.
    [In Postscript (gzip'ed)]

  2. K. Y. Yun and A. E. Dooply, "Pausible clocking based heterogeneous systems," IEEE Transactions on VLSI Systems, vol. 7, no. 4, pp. 482-487, Dec. 1999.
    [In Postscript]

  3. K. W. James and K. Y. Yun, "A 40Gb/s packet switching architecture with fine-grained priorities," in Proceedings of the Eighth International Conference on Computer Communications and Networks, Boston, Massachusetts, Oct. 1999.

  4. V. L. Do and K. Y. Yun, "A scalable priority queue manager architecture for output-buffered ATM switches," in Proceedings of the Eighth International Conference on Computer Communications and Networks, Boston, Massachusetts, Oct. 1999.
    [In Postscript (gzip'ed)]

  5. W.-C. Chou, P. A. Beerel, and K. Y. Yun, "Average-case technology mapping of asynchronous burst-mode circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 10, pp. 1418-1434, Oct. 1999.

  6. S. Chakraborty, K. Y. Yun, and D. L. Dill, "Timing analysis of asynchronous systems using time separation of events," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 8, pp. 1061-1076, Aug. 1999.
    [In Postscript]

  7. S. Rotem, K. Stevens, R. Ginosar, P. Beerel, C. Myers, K. Yun, R. Kol, C. Dike, M. Roncken, and B. Agapiev, "RAPPID: an asynchronous instruction length decoder," in Proceedings of the 1999 International Symposium on Advanced Research in Asynchronous Circuits and Systems, Barcelona, Spain, Apr. 1999, pp. 60-70.

  8. A. E. Dooply and K. Y. Yun, "Optimal clocking and enhanced testability for high-performance self-resetting domino pipelines," in Proceedings of the Twentieth Anniversary Conference on Advanced Research in VLSI, Atlanta, Georgia, Mar. 1999, pp. 200-214.
    [In Postscript]

  9. K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: part I (specification and hazard-free implementations)," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 101-117, Feb. 1999.
    [In Postscript]

  10. K. Y. Yun and D. L. Dill, "Automatic synthesis of extended burst-mode circuits: part II (automatic synthesis)," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 118-132, Feb. 1999.
    [In Postscript]

  11. S. Chakraborty, D. L. Dill, and K. Y. Yun, "Min-max timing analysis and its applications to asynchronous circuits," Proceedings of the IEEE, vol. 87, no. 2, pp. 332-346, Feb. 1999.
    [In Postscript]

  12. K. Y. Yun and A. E. Dooply, "Optimal evaluation clocking of self-resetting domino pipelines," in Proceedings of the 1999 Asia and South Pacific Design Automation Conference, Hong Kong, Jan. 1999, pp. 121-124.
    [In Postscript]

  13. K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. E. Dooply, and J. Arceo, "The design and verification of a high-performance low-control-overhead asynchronous differential equation solver," IEEE Transactions on VLSI systems, vol. 6, no. 4, pp. 643-655, Dec. 1998.
    [In Postscript]

  14. K. Y. Yun, S. Chakraborty, K. W. James, R. Fairlie-Cuninghame, and R. L. Cruz, "A self-timed real-time sorting network," in Proceedings of the 1998 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Austin, Texas, Oct. 1998, pp. 427-434.
    [In Postscript]

  15. K. Y. Yun, B. Lin, D. L. Dill, and S. Devadas, "BDD-based synthesis of extended burst-mode controllers," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 9, pp. 782-792, Sept. 1998.
    [In Postscript]

  16. V. L. Do and K. Y. Yun, "A low-power VLSI architecture for full-search block-matching motion estimation," IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 4, pp. 393-398, Aug. 1998.
    [In Postscript]

  17. S. Chakraborty, K. Y. Yun, and D. L. Dill, "Practical timing analysis of asynchronous systems using time separation of events," in Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, Santa Clara, California, May 1998, pp. 455-458.
    [In Postscript]

  18. K. W. James and K. Y. Yun, "Average-case optimized transistor-level technology mapping of extended burst-mode circuits," in Proceedings of the 1998 International Symposium on Advanced Research in Asynchronous Circuits and Systems, San Diego, California, Mar. 1998, pp. 70-79.
    [In Postscript]

  19. W. Chou, P. A. Beerel, R. Ginosar, R. Kol, C. J. Myers, S. Rotem, K. Stevens, and K. Y. Yun, "Average-case optimized technology mapping of one-hot domino circuits," in Proceedings of the 1998 International Symposium on Advanced Research in Asynchronous Circuits and Systems, San Diego, California, Mar. 1998, pp. 80-91.
    [In Postscript]

  20. K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. E. Dooply, and J. Arceo, "The design and verification of a high-performance low-control-overhead asynchronous differential equation solver," in Proceedings of the 1997 International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eindhoven, The Netherlands, Apr. 1997, pp. 140-153.
    [In Postscript]

  21. S. M. Nowick, K. Y. Yun, P. A. Beerel, and A. E. Dooply, "Speculative completion detection for the design of high-performance asynchronous dynamic adders," in Proceedings of the 1997 International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eindhoven, The Netherlands, Apr. 1997, pp. 210-223.
    [In Postscript]

  22. S. Chakraborty, D. L. Dill, K. Y. Yun, and K.-Y. Chang, "Timing analysis for extended burst-mode circuits," in Proceedings of the 1997 International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eindhoven, The Netherlands, Apr. 1997, pp. 101-111.
    [In Postscript]

  23. K. Y. Yun, P. A. Beerel, and J. Arceo, "High-performance two-phase micropipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits," IEE Proceedings-Circuits, Devices and Systems, vol. 143, no. 5, pp. 282-288, Oct. 1996.

  24. K. Y. Yun and R. P. Donohue, "Pausible clocking: A first step toward heterogeneous systems," in Proceedings of the 1996 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Austin, Texas, Oct. 1996, pp. 118-123.
    [In Postscript]

  25. K. Y. Yun, "Automatic synthesis of extended burst-mode circuits using generalized C-elements," in Proceedings of the 1996 European Design Automation Conference, Geneva, Switzerland, Sept. 1996, pp. 290-295.
    [In Postscript]

  26. P. A. Beerel, K. Y. Yun, and W. Chou, "A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits," in Proceedings of the 1996 European Design Automation Conference, Geneva, Switzerland, Sept. 1996, pp. 284-289.
    [In Postscript]

  27. K. Y. Yun, P. A. Beerel, V. Vakilotojar, A. E. Dooply, and J. Arceo, "A low-control-overhead asynchronous differential equation solver," in Proceedings of the 22nd European Solid-State Circuits Conference, Neuchatel, Switzerland, Sept. 1996, pp. 352-355.
    [In Postscript]

  28. K. Y. Yun, P. A. Beerel, and J. Arceo, "High-performance asynchronous pipeline circuits," in Proceedings of the 1996 International Symposium on Advanced Research in Asynchronous Circuits and Systems, Aizu-Wakamatsu, Fukushima, Japan, Mar. 1996, pp. 17-28.
    [In Postscript]

  29. P. A. Beerel, K. Y. Yun, and W. Chou, "Optimizing average-case delay in technology mapping of burst-mode circuits," in Proceedings of the 1996 International Symposium on Advanced Research in Asynchronous Circuits and Systems, Aizu-Wakamatsu, Fukushima, Japan, Mar. 1996, pp. 244-260.
    [In Postscript]

  30. P. A. Beerel, K. Y. Yun, S. M. Nowick, and P. Yeh, "Estimation and bounding of energy consumption in burst-mode control circuits," in Proceedings of the 1995 IEEE/ACM International Conference on Computer Aided Design, San Jose, California, Nov. 1995, pp. 26-33.
    [In Postscript]

  31. K. Y. Yun and D. L. Dill, "A high-performance asynchronous SCSI controller," in Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Austin, Texas, Oct. 1995, pp. 44-49.
    [In Postscript]

  32. K. Y. Yun, B. Lin, D. L. Dill, and S. Devadas, "Performance-driven synthesis of asynchronous controllers," in Proceedings of the 1994 IEEE/ACM International Conference on Computer Aided Design, San Jose, California, Nov. 1994, pp. 550-557.
    [In Postscript]

  33. K. Y. Yun and D. L. Dill, "Unifying synchronous/asynchronous state machine synthesis," in Proceedings of the 1993 IEEE/ACM International Conference on Computer Aided Design, Santa Clara, California, Nov. 1993, pp. 255-260.
    [In Postscript]

  34. K. Y. Yun, D. L. Dill, and S. M. Nowick, "Practical generalizations of asynchronous state machines," in Proceedings The European Conference on Design Automation with The European Event in ASIC Design, Paris, France, Feb. 1993, pp. 525-530.
    [In Postscript]

  35. K. Y. Yun and D. L. Dill, "Automatic synthesis of 3D asynchronous state machines," in Proceedings of the 1992 IEEE/ACM International Conference on Computer Aided Design, Santa Clara, California, Nov. 1992, pp. 576-580.
    [In Postscript]

  36. K. Y. Yun, D. L. Dill, and S. M. Nowick, "Synthesis of 3D asynchronous state machines," in Proceedings of the 1992 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, Massachusetts, Oct. 1992, pp. 346-350.
    [In Postscript]

  37. S. M. Nowick, K. Y. Yun, and D. L. Dill, "Practical asynchronous controller design," in Proceedings of the 1992 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, Massachusetts, Oct. 1992, pp. 341-345.
    [In Postscript]

  38. K. Y. Yun, Synthesis of asynchronous controllers for heterogeneous systems, PhD thesis, Stanford University, 1994. Technical Report CSL-TR-94-644.
    [In Postscript]

Back to Dr. Yun's Home Page